1. Field of Invention
This invention relates to methods of forming semiconductor structures.
2. Description of Related Art
Semiconductor structures may be formed by bonding two wafers together and cutting the bonded wafers into individual semiconductor structures. For example, thermal ink jet printheads conventionally include a heater plate and a channel plate. The heater plate includes a surface having a plurality of resistive heating elements and passivated addressing electrodes. The surface of the heater plate having a plurality of resistive heating elements and passivated addressing electrodes is known as the electronic plane. A polymer layer containing fluidic passageways may be photopatterned on the surface of the heater wafer. Fluidic passageways or channels may also be formed on a surface of the channel plate. Several hundred corresponding heater die and channel die typically reside on the two respective wafers. The two corresponding bonded die are known collectively as a die module.
Conventionally, thermal ink jet die modules are formed by producing sets of heating element arrays and associated addressing electrodes on a first silicon wafer. Alignment marks are placed on the first silicon wafer at predetermined locations by any suitable process, such as by deposition and patterning of a metallic layer. Corresponding sets of fluidic passageways and associated manifolds are produced in a second silicon wafer. Alignment features are etched in the second silicon wafer at corresponding predetermined locations. The two wafers are aligned via the respective etched and metallized alignment features on the two wafers, for example by using infrared illumination to view the alignment features on the two wafers. The two wafers are then bonded together and diced into many separate die modules.
Cutting or dicing bonded wafers is often an important step in forming the individual semiconductor structures. The performance of the semiconductor structure may ultimately depend upon the accuracy of the dicing cut.
For example, when forming individual thermal ink jet die modules, a dicing blade is used to dice the bonded silicon wafers into individual die. Dicing cuts are made to separate the various rows and columns of the two dimensional array of die modules. Dicing fiducial marks on the heater wafer are used as reference marks for positioning the cuts. In a side shooting printhead, some dicing cuts are made across grooves that form individual jetting channels. These grooves are formed either by photopatterning the polymer layer on the heater wafer or by etching the surface of the channel wafer. In these dicing cuts, the dicing blade creates a smooth nozzle surface having no chip defects. The position of the nozzle dicing cut is important because the dicing position affects the fluid dynamics of ink ejected from the nozzles. For example, the distance from the bubble nucleating heater to the front of the device affects the drop velocity and the drop volume. Ultimately, the quality of printed documents is impacted by the position of the nozzle dicing cut. Thus, improved control over cut position would achieve better jetting performance.
Controlling the cut position on bonded silicon wafers depends on the positional or placement accuracy of the dicing saw used to create the nozzle surface. The cut placement accuracy depends on various factors, including index accuracy, operator/optical error, offset error, dicing blade cut consistency and angle of the cut. Cut placement accuracy can be affected by side forces generated when the dicing blade passes through the bonded wafer pair. These side forces can cause a row of die mounted on a material, such as a dicing tape, to shift on the material by as much as several microns. Cut placement accuracy can also be affected by blade bending, which can increase over time as the materials forming the dicing blade become fatigued due to repeated flexing. As blade bending and blade wear increase, the top edge of the cut no longer reflects the cut edge that is located, for example, at the electronic plane. The top edge of the cut may, in some instances, be 15 xcexcm out of position from the cut at the electronic plane.
Previously, for bonded wafer pairs, a single set of dicing fiducials on the electronic plane has been made visible by etching a corresponding opening all the way through the channel wafer. The conventional method for dicing such wafer pairs includes operating the dicing saw in an open loop mode using the single set of fiducials to line up the first cut. That is, the position of the dicing saw is not adjusted based on the previous cut and/or measurements made during the current cut. In fact, conventionally for bonded wafer pairs, the dicing saw can not make adjustments based on the previous cut because the cut position at the electronic plane can not be viewed optically. Although one could etch holes all the way through the channel wafer to view alignment features in each row to be diced, there are two problems with this approach: 1) The orientation dependent etching of the silicon channel wafer does not etch holes perpendicular to the wafer, but at an angle. In order to etch a hole large enough to see the dicing fiducial, the actual silicon real estate required is quite large, so that space is consumed that could otherwise be used for making die. 2) Dicing through the large etched holes can cause the blade to deflect, causing additional error in the cut position.
Fully automatic saws are well known in the industry, but have not been used in dicing bonded wafer pairs because of the inability of fully automatic saws to optically view the cut position at the electronic plane. Some known dicing saws, such as the Disco 640 and the Kulicke and Soffa 980, have pattern recognition, which enables the saw to locate reference targets and align the dicing blade with the wafer fully automatically in the X,Y,Z and xcex8 directions. In addition, some saws have kerf check software, which enables these dicing saws to determine how far from the dicing target the actual cut was made. This value is used to calculate a Y-offset value for error correction for the next dicing cut. This combination of features enables the saw to correct for cut placement errors fully automatically and to provide more accurate cuts than the equivalent saw used in an open loop mode. However, these features are not presently useable in bonded wafer dicing because the row-by-row dicing targets are hidden from view at the electronic plane by the channel wafer.
An alternative approach is views the electronic plane through the silicon channel wafer using an infrared camera. However, this approach has not allowed the complete use of the features of fully automatic saws. While the dicing reference targets can be viewed at infra-red wavelengths, the dicing cut edge can not be viewed. This is because the bevel produced by the dicing blade casts a broad shadow over the cut edge at the electronic plane. The shadow effectively masks the view of the cut edge, preventing the cut position from being accurately determined.
This invention provides systems and methods that allow for improved accuracy in forming individual semiconductor devices from bonded wafers.
This invention separately provides systems and methods that allow using certain features of fully automatic dicing saws that previously were not capable of being used in dicing bonded semiconductor wafers.
This invention separately provides systems and methods that allow for fully automatic dicing saws to be used in a closed-loop mode.
This invention separately provides systems and methods that allow for improved control over cut position when cutting thermal ink jet printhead nozzle faces to achieve improved ink jetting performance.
This invention separately provides systems and methods that allow fully automatic dicing saws to optically view dicing reference targets at the electronic plane of bonded semiconductor wafers.
This invention separately provides systems and methods that prevent coolant from obscuring dicing reference targets at the electronic plane of bonded semiconductor wafers.
This invention separately provides systems and methods for forming a semiconductor structure from a first wafer and a second wafer.
Various exemplary embodiments of the methods according to this invention comprise one or more of removing a first portion of a lower surface of the first wafer; bonding the lower surface of the first wafer to an upper surface of the second wafer; removing a second portion on an upper surface of the first wafer, such that an opening is formed in the first wafer that exposes at least one alignment reference target on the upper surface of the second wafer; optionally coating at least a portion of at least one of the surfaces that form the opening; and dicing the bonded first wafer and second wafer using the exposed at least one alignment reference target to form a semiconductor structure.
These and other features and advantages of the invention are described in, or are apparent from, the following detailed description of various exemplary embodiments of the systems and methods according to this invention.